Nick Armstrong

Things I've Built

STM32, Embedded C++, CAN, DMA

Led firmware development for distriuted STM32 system of plug-and-play nodes, using a shared CAN bus to synchronize behaviour with the drone state.
Used the STM32 HAL to control DMA, interrupts, and hardware timers to communicate with board peripherals while minimizing overhead usage.
Wrote modular, reusable, and highly maintainable embedded C++, making architectural decisions to decouple separate components.
CAN LED network whitepaper

Rust, Assembly, SIMD, ESP32

Handwritten image processing kernels in assembly, using SIMD and minimizing data dependencies to eliminate pipeline hazards and 4x throughput.
Fine-tuned and quantized image embeddings model in TensorFlow, optimizing for high-throughput ESP-NN inference.
Developed a PnP RANSAC pipeline for robust camera localization, rejecting dynamic outliers.

Trajectory Planning, Kalman Filtering, PID

Use RProp numerical optimization to generate optimal Hermite spline trajectories.
Developed Kalman-filter based odometry and IMU-based sensor fusion to adaptively react to disturbances.
Deployed to a Linux device at FRC robotics competitions, enabling complex autonomous routes to score more points.

Verilog, TinyTapeout

Built a FSM-based SPI peripheral, using best practices such as cascading flip-flops to avoid metastability issues.
Implemented an in-hardware PI controller using accumulators and power-of-2 coefficients to eliminate unnecessary MAC units.
Implemented motion planning math using a FSM, saving 4-5x area over the naive MACs and divide units.

Rust, Git, GitHub

Developed a compiler for a functional programming language using techniques including specialization, unboxing, and defunctionalization to maximize performance.
Used the Rust type system to guarantee correctness of program transformations.

Sept. 2025 – Dec. 2025

Built a thread-safe SPI HAL using fine-grained locking and a deterministic job queue to arbitrate concurrent hardware access.
Accelerated FPGA bring-up, analyzing Verilog & register maps to write bare-metal driver code, bypassing hardware defects.
Architected a custom co-operatively scheduled RTOS, providing production-ready multitasking to an ultra low power MCU using less than 3 KB of ROM.
Led discussions and delivered presentations to drive the design of a hardware-agnostic non-volatile memory stack, establishing a unified API for EEPROM, OTPM, and ReRAM.
Implemented a high-performance CRC library, optimized with lookup tables and assembly-level tuning, performing as few as 1.25 memory loads per byte.
Researched the JEDEC SFDP spec to implement a flash controller with dynamic runtime detection of device capabilities.

90+ member student design team · Sept. 2024 – Present

Managed a 9-member team developing software to power a distributed network of microcontrollers on a unified CAN bus, using a decentralized leader election algorithm for a plug-and-play Flight Lighting System.
Architected software to use embedded hardware acceleration including DMA, interrupts, and hardware timers to optimize performance.
Debugged distributed software using GDB and network capture tools like logic analyzers and oscilloscopes.
Led software development as project manager using project boards and PR-based workflows.

May 2026 – Aug. 2026

Jan. 2025 – Apr. 2025

Built a fault-tolerant parser for a binary logging file format, bypassing corrupted payloads to ensure reliable testing while tracking down bugs in other teams' logging tools using Wireshark.
Redesigned a concurrent logging library using state machines to ensure thread safety and clarity.
Analyzed a massive codebase to create specialized SELinux policy files and improve security.
Developed an embedded C++ hardware abstraction layer to enable testing via gTest and gMock.